`timescale 1ns / 1ps

module tb_romLoader();

parameter N = 32;
parameter D_WIDTH = 8;

reg rst;
reg clk;
wire [D_WIDTH-1: 0] out;
reg  o_rdy;
wire o_vld;

always #5 clk = ~clk;

integer i;

initial
begin
    clk = 0;
    rst = 1;
    o_rdy = 0;
    #20;
    rst = 0;
    #10;
    
    for (i = 0; i < N; i = i + 1)
    begin
        // o_rdy = 1;
        o_rdy = {$random()} % 2;
        #10;
    end

    $display("Done.");
    $stop;
end

ROM_Loader
#(
    .WIDTH(D_WIDTH),
    .DEPTH(16),
    .MEM_FILE("testmem.mem"),
    .MEM_TYPE("auto"),
    .MEM_LATENCY(2)
) inst_loader
(
    .clk(clk),
    .rst(rst),

    .o_vld(o_vld),
    .o_rdy(o_rdy),
    .o_data(out)
);

endmodule
